Hence my question: how does one generate all object files in a separate directory at once (by this I mean perform the compilation of all sources files in one rule) while making sure that if a source file didn't change the associated object file should not be regenerated. The second makefile works as expected but objects files are being rebuilt again which defeats another purpose of using make: only recompile those source files that changed from the last compilation. This can be seen by checking the timestamps on new object files after running make again. # This works as expected but it appears to me like make is generating all the objects files even though source files did not change. So I changed my makefile to the following: sources = $(shell find src/ -name ".c") Regardless of that, checking the values of and $(word 2, $^) in the $(objects) target shows that only one file is being considered even though I have multiple files. I guessed this might have something to do with GCC only being able to generate one object file at a time. $(foreach dir, $(objects_dirs), $(shell mkdir -p $(dir)))įor the makefile above, only one object file was being generated. # This is where things aren't working as expected Objects = $(subst src/, build/, $(patsubst %.c, %.o, $(sources))) # This variable has the paths to the objects files that will be generated in the build directory Objects_dirs = $(subst src/, build/, $(dir $(sources)) # This variable is used by the build rule to create directories for objects files prior to compilation The first attempt was as follows: sources = $(shell find src/ -name ".c") Please note also that under mylib there are subdirectories. I want the objects files to end up in build/mylib. I have multiple sources in a directory say src/mylib. Similarly, If you want to remove all the non-required object or executable files before every cycle of compilation, you can add a target clean to your Makefile.This question is different from the one at makefiles - compile all c files at once in the sense that I have one extra requirement: I want to redirect all the object files in a separate directory. Then this command would scan the Makefile, build (if required) the dependencies of test and then execute the command to build test itself. For example, if you specify the following command : make test
#How to write a makefile for multiple files how to
This command accepts a target as an argument and looks for a file named 'Makefile' to understand how to build that target. Now, one would ask, how to use these targets? Well, these are used through the 'make' command. c files, and can be produced through the respective commands mentioned below them.
c files but use a single command to recompile. Now, suppose you add a simple printf debug line in one of the.
But, what if you somehow loose this command or switch to another system? Will you again type the long command?Īlso, suppose your project grows into a big project that contains hundreds of files, and takes 5-10 minutes to compile. Many would argue that they will extend the existing command by adding the names of those new files.
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